TCM 3105
Based on Texas Instruments Interface Circuits book

Features:

Single chip FSK modem.
Meets CCITT V23 standard:

Meets Bell 202 standards:
Full duplex operation up to 1200 bauds
Transmit and receive in 4 wire mode.
Carrier detect level adjustment and carrier fail output.
On chip Transmit/Receive filtering and group delay equalisation.
Reliable CMOS silicon gate technology.
16 pin DIL package (pin to pin compatible with TCM 3101).
Local copy/loop back test capability.


General description:

The TCM3105 is a versatile single chip Frequency Shift Keyed (FSK) voiceband modem. It uses silicon gate CMOS technology with switched capacitor filtering techniques.It is pin programmable (using V23 operation and is fully reversible, thereby allowing both forward and backward channels to be used simultaneously).

The transmitter is a programmable frequency synthesizer which provides two output frequencies (on TXA), representing the "Marks" and "Spaces" ot the digital signal present on the TXD input.

The receive section is responsible tor the demodulation ot the analogue signal appearing at the RXA input and is based on the principle of frequency to voltage conversion. This section contains a Group Delay Equaliser (to correct phase distortion). Automatic Gain Control, Carrier Detect Level adjustment and Bias Distortion adjustment, thereby optimising performance and giving the Iovest possible bit error rate.

Carrier detect intormation is given to the system by means ot the carrier detect circuitry which sets a flag on the CDT output if the level ot received in band energy falls below a value set on the CDL input for a specified minimum duration.


Important application notes

1. AUTOMATIC GAIN CONTROL

Automatic gain control will initially be set to maximum gain when no signal is received The gain will then be reduced in steps (up to 16, it high level is received) on each consecutive mark received.

Consequently an adjustment delay up to 11 ms should be provided by a continuous "Mark" signal (N.B. 11 ms would be required in the case of peak voltage of input waveform to AGC being at maximum dynamic range of AGC).

This procedure will normally be followed such that the adjustment delay occurs along with carrier detect and precautions should be taken when deciding upon setting up and testing method.

2. CDL APJUSTMENT

For optimum results. CDL should be adjusted to the following ratios of VDD:

3. RXB ADJUSTMENT PROCEDURE

The choice of d-c voltage on the RXB input (pin 7), determines the decision threshold of the final comparator stage of the receive circuitry. Correct adjustment is achieved by :


Electrical data
Pin description
Circuit description
Frequency and modes