Receive/transmit modes of operations

FIG. 5

CCITT V23
TRS
TXR1
TXR2
TRANSMITTED
BIT RATE (b/s)
RECEIVED
BIT RATE (b/s)
CLK
FREQUENCY(KHz)
0
0
0
1200
1200
19.11
1
0
0
1200
75
19.11
0
0
1
600
75
9.56
1
0
1
600
600
9.56
0
1
0
75
1200
19.11
1
1
0
75
600
9.56
0
1
1
75
75
1.19
BELL202
TRS
TXR1
TXR2
TRANSMITTED
BIT RATE (b/s)
RECEIVED
BIT RATE (b/s)
CLK
FREQUENCY(KHz)
CLK*
0
0
1200
1200
19.11
CLK 8
0
1
1200
150
19.11
CLK 8
0
1
1200
5
19.11
CLK
1
0
150
1200
19.11
CLK
1
1
150
150
2.39
See note 1
1
See note 1
5
1200
19.11
1
1
1
Transmit
disabled
1200
19.11

Clock output must be inverted and connected to TRS input.
NOTE 1 : In this mode the modulation is controlled by the TRS and TXR2
TRS = CLK & TXR2 = 0 TXD = 1 TXA = 387Hz
TRS = 1 & TXR2 = 1 TXD = 1 or 0, TXA = 0Hz

Frequency assignment

FIG.6

CCITT V23
TRANSMITTED
TXD
BIT RATE b/s
TRANSMITTED
FREQUENCY Hz
75
1
M
390
75
0
S
450
600
1
M
1300
600
0
S
1700
1200
1
M
1300
1200
0
S
2100

BELL 202
TRANSMITTED
TXD
BIT RATE b/s
TRANSMITTED
FREQUENCY Hz
150
1
M
387
150
0
S
487
1200
1
M
1200
1200
0
S
2200
5
See note 1
M
387
S
0

NOTE 1 : In this mode the modulation is controlled by the TRS and TRX2 inputs