PIN DESCRIPTION
(TXD) Transmitter Digital Input
The data to be transmitted is presented to this input. The data should be positive true logic, a logic "1" being a mark and a logic "0" a space. This data may be totally asynchronous and has no speed restriction. A data rate from zero to the transmit speed selected is acceptable.
(TXA) Transmitter Analogue Output
The output of the FSK modulaled signal appears on this pin. The voltage swing of this analogue signal is dependent on the power supply. This output signal is referred to the internal reference voltage and hence TXA must be a.c. coupled.
(TXR1, TXR2, TRS) Receive Transmit Mode Select Inputs
The logic state of these inputs is internally decoded to place the modem into the required mode. A transmitter disable mode is also available. Pin TRS is effectively a three state input, since it can receive a high level (1), a low level (0) or the clock output (CLK) See fig.5 for possible modes.
(RXA) Receiver Analogue Input
The modulated analogue signal is received at this pin. Due to the single supply of the TCM3105, this input is internally biased by an internal reference voltage and must be a.c. coupled.
(AXD) Receiver Digital Output
This output provides the demodulated received data in positive true logic, a received mark frequency being a "1" and a received space frequency a "0".
(RXB) Receiver Bias Adjust Input
This input allows external adjustment of the decision threshold of the final comparator stage and hence the bias distortion of the output data. This adjustment is independent of the receive mode.
(CDT) Carrier detector Output
This output provides a carrier detect flag for the system. A high logic level signals the presence of in-band energy for a time longer than the minimum specified duration and a low level signals the absence of in-band energy for a time longer than the minimum specified duration.
(CDL) Carrier Detect Level Adjust Input
This input allows external adjustment of the carrier level threshold via an external potentiometer.
(OSC1, OSC2) Clock Oscillator Input/Output
These pins are the input and output of the on-chip clock oscillator and are typically connected to a 4.4336 MHz PAL quartz crystal. An external clock may be used by connecting it to OSC1 and leaving OSC2 open circuit.
(CLK) Clock Output
This output provides a continous clock signal at 16 times the highest selected (transmit or receive) bit rate. This clock is intended for external use such as UART control and as an input signal of the TRS input after a correct division (See Fig. 5 for possible modes).
(RXT) Receiver Test Output
This output is an intermediate limiter output.
(VDD,VSS) Power Supply Inputs
The pins VDD and VSS must be connected to the correct voltage supplies. VDD is the positive supply as specified and VSS is the negative supply voltage, normally ground, which is connected to the substrate.
